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QPHY-DDR3 Software Option

917717 Rev C 43

Figure 21: tIS illustration (Figure 111 from JESD79-3E)

Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of

VREF(dc) and the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined

as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max.

Jedec JESD79-2E Specific Note 9 (page 95 to 100) with tables 46 and 47 explain the limit compensation

versus the slewrate of the measured signals. Timing limits are initially specified for input slewrate of 1V/ns

for single-ended signals and 2V/ns for differential signal (for DQS and CK).

tIPW, Control and Address Input pulse width for each input

Pulse width of a input signal is defined as the width between the first crossing of Vref(dc)

and the consecutive crossing of Vref(dc).

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