QPHY-DDR3 DDR3 Serial Data Operator’s Manual 917717 Revision C – July 2011 Relating to the Following Release Versions: • Software Option Rev
10 917717 Rev C Figure 2. Differential probe properly connected to the fixture (Solder-In configuration) Probe Calibration Menu
QPHY-DDR3 Software Option 917717 Rev C 11 The probe calibration menu can be accessed from the Vertical drop-down menu or from the channel dialog:
12 917717 Rev C 1. Connect the probe to the PCF200 Fixture. 2. Press the Deskew Only button in the appropriate row representing the channel to b
QPHY-DDR3 Software Option 917717 Rev C 13 BASIC FUNCTIONALITY The functionality is extracted from JEDEC Standard No. JESD79-3D, section 3. The DDR
14 917717 Rev C READ Burst Operation During a READ or WRITE command, DDR3 supports BC4 and BL8 on the fly using address A12 during the READ or WR
QPHY-DDR3 Software Option 917717 Rev C 15 WRITE Burst Operation During a READ or WRITE command, DDR3 supports BC4 and BL8 on the fly using address
16 917717 Rev C USING QUALIPHY DDR3 QualiPHY DDR3 guides the user, step-by-step, through each of the source tests described in JEDEC Standard No.
QPHY-DDR3 Software Option 917717 Rev C 17 Figure 8. Report menu in QualiPHY General Setup
18 917717 Rev C See the QualiPHY Operator’s Manual for more information on how to use the QualiPHY framework. Figure 9. The Test Report includes
QPHY-DDR3 Software Option 917717 Rev C 19 Oscilloscope Option Key Installation An option key must be purchased to enable the QPHY-DDR3 option. Call
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20 917717 Rev C QualiPHY tests the oscilloscope connection after clicking the Start button. The system prompts you if there is a connection probl
QPHY-DDR3 Software Option 917717 Rev C 21 Figure 10. QualiPHY main menu and compliance test Standard selection menu
22 917717 Rev C 4. Click the Configuration button in the QualiPHY main menu: 5. Select a configuration from the pop-up menu: Figure 11. QualiP
QPHY-DDR3 Software Option 917717 Rev C 23 Customizing QualiPHY The predefined configurations in the Configuration screen cannot be modified. Howeve
24 917717 Rev C Once a custom configuration is defined, script variables and the test limits can be changed by using the Variable Setup and Limits
QPHY-DDR3 Software Option 917717 Rev C 25 QPHY-DDR3 Operation After pressing Start in the QualiPHY menu, the software instructs how to set up the t
26 917717 Rev C QPHY-DDR3 TEST CONFIGURATIONS Configurations include variable settings and limit sets as well, not just test selections. See the
QPHY-DDR3 Software Option 917717 Rev C 27 • VOL(ac/dc) • VSWING • tQSH • tQSL • tHP, tQHS • tLZ(DQ) • tLZ(DQS) • tRPRE • tDQSS • tDQSH •
28 917717 Rev C 3) CKdiff-DQse-DQSdiff 1333 Read Burst (3 Probes) This configuration runs all of the tests that are run on read bursts of the DDR3
QPHY-DDR3 Software Option 917717 Rev C 29 • tIH (base + derated) • tIPW 7) CKdiff-DQse-DQSp-DQsn (4 probes test, each DQS signal probed single en
QPHY-DDR3 Software Option 917717 Rev C 3 TABLE OF CONTENTS INTRODUCTION TO QPHY-DDR3 ...
30 917717 Rev C DQ Signal Name Select name of data (DQ) SUT. Choose between available DDR signal names. Default is DQ0. DQS Signal Name Select nam
QPHY-DDR3 Software Option 917717 Rev C 31 Overall Write Latency This is used to specify the Delay between DDR command (Write) to first data bit of
32 917717 Rev C Advanced Settings Clock Period per Screen Division Oscilloscope timebase and sampling rate is set to acquire the given number of
QPHY-DDR3 Software Option 917717 Rev C 33 CAS Write Latency Allows the user to specify the CAS Write Latency (CWL) used to define tCK(avg) limits (
34 917717 Rev C QPHY-DDR3 LIMIT SETS DDR3-800 This corresponds to the JEDEC JESD79-3D DDR3 standard specification limits for 800 MT/s. DDR3-1066 T
QPHY-DDR3 Software Option 917717 Rev C 35 tCL(avg), Average Low Pulse Width tCL(avg) is defined as the average low pulse width, as calculated acros
36 917717 Rev C tERR(n per), Cumulative Error tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is
QPHY-DDR3 Software Option 917717 Rev C 37 For differential signals (e.g. CK - CK#) slew rate for rising edges is measured from Vihdiffmin to Vihdif
38 917717 Rev C The local minimum must be greater than or equal to the minimum limit. The local maximum must be less than or equal to the maximum
QPHY-DDR3 Software Option 917717 Rev C 39 Measure timing from DQS at VREF to DQ rising at VIH(ac)min and falling at VIL(ac)max. Figure 17 - Data o
4 917717 Rev C Chip Select Signal Name ...
40 917717 Rev C Figure 18. Burst read operation [JESD79-3D figure 28] This is a measure similar to tDQSS but on the Read frame (the result can be
QPHY-DDR3 Software Option 917717 Rev C 41 Write Bursts tDQSS, DQS latching rising transitions to associated CK edge CK rising edge at VREF level to
42 917717 Rev C tDSS, DQS Falling Edge to CK Setup Time Time from DQS falling edge at VREF level to CK rising edge at VREF level, see Figure 22.
QPHY-DDR3 Software Option 917717 Rev C 43 Figure 21: tIS illustration (Figure 111 from JESD79-3E) Setup (tIS) nominal slew rate for a rising signa
44 917717 Rev C VIX(ac), AC Differential Input Cross Point Voltage The typical value of VIX(ac) is expected to be about 0.5 x VDDQ of the transmi
QPHY-DDR3 Software Option 917717 Rev C 5 VIH(dc), minimum DC input logic high ...
6 917717 Rev C FIGURES Figure 1. READ Burst Operation RL = 5 (AL = 0, CL = 5, BL8) [JESD79-3D Figure 25] ... 14 Figure 2. READ
QPHY-DDR3 Software Option 917717 Rev C 7 INTRODUCTION TO QPHY-DDR3 QPHY-DDR3 is an automated test package performing all of the real time oscillosc
8 917717 Rev C DDR3 MEASUREMENT PREPARATION Before starting any test or data acquisition, the oscilloscope must be warmed for at least 20 minutes
QPHY-DDR3 Software Option 917717 Rev C 9 Figure 1. PCF200 Deskew Fixture A SMA male to BNC male 50-ohm cable is required to perform the calibratio
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